Acorn MEMC Datasheet

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The Memory Controller MEMC datasheet has 74 illustrated pages
Part number 0460,019 Issue 1.0
30th September 1986

The Memory Controller (MEMC) acts as thc interface between the ARM (Acorn RISC Machine) processor,
Video Controller (VIDC), I/O Controllers (including IOC), memories (ROM) and Dynamic
memory devices (DRAM), providing all the critical system timing signals.

Up to 4MBytes of DRAM may be connected to MEMC, which provides all signals and refresh operations
for a wide variety of standard DRAMs. A Logical to Physical Address Translator maps the Physical
memory into a 32MBylc Logical address space (with three levels of protection) allowing Virtual Memory
and Multi-Tasking operations zo be implemented. Fast "page modo" DRAM acccsscs are used to maximise
memory bandwidth.

MEMC supports Direct Memory Access (DMA) read opcralions with a set of programmable DMA Address
Generators, which provide a circular buffer for Video data, a linear buffer for Cursor data, and multiple
buffers for Sound dum.

Reference Number :

Date Published : 30th September 1986

Manufacturer : Acorn

Platform : MEMC






This exhibit has a reference ID of CH29468. Please quote this reference ID in any communication with the Centre for Computing History.

Acorn MEMC Datasheet

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