SC/MP Development System
This is a National Semiconductor Simple Cost Effective Microprocessor System (SC/MP). This is a single board microcomputer commercial development system.
Original Price: $499 - Original Date: 1976
Our Model number ISP-8P 301 NE and was very kindly donated by Mike Voss
Single-chip 8-bit microprocessor (ISP-8A/500)
Low cost microprocessor that has been designed to operate easily in multi-microprocessor configurations.
Most microprocessors are designed to always operate as bus master in any microcomputer system. SC/MP, in contrast, has the bus interface logic of a support device. it does not assume that it has any more right to a system bus than any other device. Bus request acknowledge logic coupled with bus access priority logic makes SC/MP the slave microprocessor of choice in any multi-microprocessor application.
Simple-to-use Cost-effectiv MicroProcessor
Silicon gate, P-channel Isoplanar LSI technology
Designed to fill the gap between four-bit CPUs (4004, 4040) and eight-bit microprocessors, the SC/MP features a 12-bit address bus, interfacing directly to 4 K bytes of standard memory. +5 V and -7 V volts power supply. Providing CMOS compatibility.
SC/MP is much slower than CPUs in N-Channel MOS technology. The simplest instruction takes five microcycles, each 2 us long – making the SC/MP about as fast as the 8008. Nevertheless, SC/MP should be attractive in industrial controllers in which speed is not critical.
SC/MP is a direct descendant of PACE.
Information from http://www.cpu-museum.com/SCMP_e.htm
Our model was very kindly donated by Mike Voss to gether with documentation and manuals
Manufacturer: National Semiconductor
SC/MP Development System Manuals :
Magazines RELATED to SC/MP Development System in our Library
This exhibit has a reference ID of CH4623. Please quote this reference ID in any communication with the Centre for Computing History.
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