Powertran SC84

In 1979, the British magazine Wireless World published the technical details for a "Scientific Computer". Shortly afterward the British firm Powertran Computers of Andover in Hampshire UK used this design for their kit computer, the PSI Comp 80. During the mid-1980s the designer, John Adams, published a new version of the Scientific Computer - the SC84 (Scientific Computer of 1984). It was based upon a backplane and plug-in cards and modules and was initially based around the Z80 processor. Later versions featured a Hitachi HD64180 processor, up to 512 kbytes of RAM, and a high resolution colour graphics system.

Add-ons were developed for the system, including memory expansions, floppy and hard disk interfaces, various software packages and a disk operating system, SCIDOS, which was CP/M-compatible. Version 3 of SCIDOS ran only on the HD64180 processor and took advantage of the built-in memory management unit (MMU) to page out the BIOS and operating system; this allowed more free memory for user programs. It also included structured (pathed) disk folders, an improvement over the CP/M-style single directory that the original Z80 version had.

Our SC84 is built into a Superbrain case and, together with literature and documents, was kindly donated by Mike Baron.

The images to the right show (from top to bottom): SC84 Video card, SC84 Z80 CPU card, and SC84 Floppy Disk/GPIO/Serial interface card

SC84 specification:

  • Processor: 4/6MHz Z80 processor (Hitachi HD64180 in later designs).
  • Maximum 64K-byte ram.
  • Display: Up to 32 lines of 96 characters fully programmable. Scrolling window determined by software.
  • Graphics modes: Mode 0 gives 192 by 96 pixels, mode 1 gives 192 by 192 resolution. Characters and graphics may be displayed simultaneously.
  • Input/output: Up to four single or double-sided 8, 5.25, 3.5 or 3in disc drives may be used, either single or double density.

    RS232 serial i/o data rates range from 1 to 38400baud with separate transmit/receive clocks. Synchronous serial i/o format is 5 to 8-bit auto-search and sync, or asynchronous 5 to 8-bit with 1,1.5 or 2 stop bits. RTS and CTR signals control serial data flow.

    Eight-bit parallel data input is buffered by schmitt i.cs. Eight-bit parallel output drives five U.I. loads. Three mos i/o lines operate event counters, pulse timers and Z80 interrupts. Four mos timer lines are available for timing and sound generation.

Manufacturer: Powertran
Date: 1984

This exhibit has a reference ID of CH22148. Please quote this reference ID in any communication with the Centre for Computing History.


Powertran SC84

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